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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 14 design characteristics such as metal layer densities, wire length distributions, and layout pattern geometries can be used to estimate the similarity between two designs. The flow described below employs standard cell usage as a measure of design similarity, with the objective of minimizing the difference between the target and CM-LCV standard cell usage frequencies. The second objective for the CM-LCV is that it is maxi- mally testable and diagnosable. While C-testability ensures the testability of each FUB in the array, different logical implementations of the FUBs themselves can result in varying degrees of testability. This testability is evalu- ated using gate-level fault coverage, which is defined as the number of gate-level faults detectedby a given test set divided by the total number of possible faults. Maximizing fault coverage for both the single stuck line (SSL) and input pattern (IP) fault models is used here as the specific testability objective. However, simply maximizing fault coverage alone is not enough. Suppose a specific standard cell has an unknown pr oblem that causes a fraction of instances to produce a w rong value for a specific input pattern (e.g., an IP fault). I f this IP fault is never detected for that stan- dard cell in t he CM-LCV, then by definition, this unknown problem can not be detected. This combination of a stan- dard cell an d an IP fault is called an IP fault class. These undetectabl e IP fault classes are a significant concern for test chips, whose purpose is to catch unknown issues. Thus, a final objective for the CM-LCV is to ensure that no IP fault class remains undetected. DESIGN FLOW The CM-LCV design flowof Fig. 3 beginswith the library of standard cells for a given technology. In the first step, the logical functions are extracted from the standard cell library to create a logic library. Note that a typical standard cell library contains numerous logic functions implemented as cells with varying drive strengths. For example, theremay exist a two-input NANDwith nominal drive strength (typically denoted as nand2_1x) and a two- input NANDwith twice the drive strength (e.g., nand2_2x). Both of these cells implement the two-input NAND logic function. The resulting logic library is used to repeatedly synthesize a given FUB function, resulting in a library of (different gate-level) FUB implementations. Each of these FUB implementations is examined for its standard cell usage, fault coverage, and diagnosability characteristics. A similar analysis is performed on the product design or family of designs. The standard cell usage measured from the product design(s) are used in addition to input from the designers to determine the objectives for the CM-LCV. These targeted objectives are combinedwith the data collected from the FUB implementations in the FUB library to formulate a matrix optimization problem. This problem is then fed to a solver, which identifies a set of FUBs from the library—called a FUB template—that best (continued on page 16) Fig. 3 CM-LCV design flow.