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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 21 NO. 1 12 AN AUTOMATED METHODOLOGY FOR LOGIC CHARACTERIZATION VEHICLE DESIGN Zeye Liu, Ben Niewenhuis, Soumya Mittal, Phillip Fynan, and R.D. (Shawn) Blanton Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh zeyel@andrew.cmu.edu EDFAAO (2019) 1:12-19 1537-0755/$19.00 ©ASM International ® INTRODUCTION Due to the high complexity of emerging technology nodes, fast yield ramping to shorten time-to-market is an incredible challenge. Meeting this challenge requires a design and fabrication methodology that enables yield learning tobe accomplishedusing actual silicon structures and chips. Many types of test structures exist, ranging from passive styles (e.g., via arrays and comb drives) to large, complex circuits (e.g., ring oscillators and SRAM). However, only a product-like test chip includes all the logic characteristics of an actual customer design. Fabri- cation and test of product-like test chips is a common practice for fabless companies, foundries, and integrated device manufacturers. Test chip effectiveness hinges on two critical prop- erties: testability (the ease with which defects can be detected in a design) and diagnosability (the ease with which a defect can be correctly isolated). Conventional product-like test chips, which are created by subsetting and adapting an existing product design, inherit the suboptimal testability and diagnosability properties of product designs. [1][2] Consequently, the suboptimal con- ventional test chip leads to missed or improperly diag- nosed failures, increased test chip production, increased effort for yield learning, and ultimately the possibility of lower product yield. Given the drawbacks of conven- tional test-chip approaches, the Carnegie Mellon Logic CharacterizationVehicle (CM-LCV) has been introduced. [2-4] CM-LCV DESIGN As noted in the introduction, test and diagnosis are of crucial importance for test chips used in yield learn- ing. The key insight driving the CM-LCV design is that the manufacturing process is sensitive only to the physical features of a design (i.e., its physical layout) and not the logic functionality that the layout implements. This allows for freedom to select a logical functionality (i.e., design architecture) that maximizes testability and diagnosabil- ity, provided that it canbe implementedusingproduct-like physical features. This section is therefore divided into two parts. The first section describes the testing theory that informs the CM-LCV design, while the second part provides a description of the design itself. REGULAR CIRCUIT TEST Regular circuits are a class of circuits composed of identical blocks that are interconnected in a uniform fashion and include one-dimensional arrays, convergent and divergent trees, and two-dimensional arrays. Various types of data-path circuits, including adders, multipli- ers, parity circuits, multiplexers, and decoders, have regular circuits as major components. In 1973, Friedman described the necessary and sufficient conditions for one-dimensional array circuits (without vertical outputs) to be what he called constant testable or C-testable for short. [5] A regular circuit is C-testable if every block-level input pattern (IP) fault [6] can be detected with a constant number of test patterns, independent of circuit size. In other words, a C-testable circuit implies that the function of every circuit block can be exhaustively verified with a fixed number of test patterns. Necessary and sufficient C-testability conditions for one-dimensional arrays with vertical outputs [7] and tree circuits [8] have been derived. However, necessary and sufficient conditions for two- dimensional array C-testability remain an open problem despite extensive studies. [9-12] In addition to the number of tests being fixed, the cardinality of the constant test set tends to be minimal or near minimal. A ripple-carry adder (RCA) composed of full-adders is probably the best-known example of a regular circuit. It is also C-testablewith just eight tests, the