November_EDFA_Digital

edfas.org 63 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 is all the design-related data (e.g., standard cell/core/ memory usage, statistics and physical locations, transis- tor types and configurations, design-for-manufacturing scoring results, etc.) that are typically stored in separate databases. Another vital piece of information available to foundries is the historical yield-learning information, such as systematic defect signatures, FA reports, process or design fixes on prior products, and technologies. It is usually not practical to store such historical yield-learning information in easily retrievable databases along with other aforementioned data types. In most cases, just a simple lookup and correlation of scan diagnosis datawith wafer-processingdata, coupledwithaccess tohistorical FA results, can serve as a surprisingly better filter than more complex statistical noise-reduction techniques used in volume diagnosis. There is a compelling case for the need for a fast, flex- ible, and scalable infrastructure that enables bringing various types of fab manufacturing process, test, and design data to enable rapid FA, leading to fast root-cause identification. We built such a flexible infrastructure using the Python programming language and extensively lever- aging open-source analysis engines. Our infrastructure brings together all the aforementioned data types. We routinely use this infrastructure and have (1) signifi- cantly reduced wasted FA requests by focusing only on high-yield-impacting failure types and not repeatedly submitting FA requests for known failure types, and (2) significantly improved the precision of the locations we request our FA teams to focus on, which has resulted in rapid root-cause identification. ABOUT THE AUTHORS Rao Desineni is currently a Distinguished Member of the Technical Staff/Director of Design Enablement at GLOBALFOUNDRIES, where his responsibilities include plug-in developer’s kit vali- dation, digital design reference flows, and design for test. Prior to joining GLOBALFOUNDRIES, Dr. Desineni was with IBM for six years in the role of integrated circuit yield manager for IBM’s 300 mm manufacturing fab. He received his Ph.D. and M.S. degrees in electrical and computer engineering fromCarnegie Mellon University in 2006. Dr. Desineni has broad research interest in the areas of chip design, manufacturing, and test. He currently holds 7 U.S. patents and has more than 30 research publications in IEEE and ASM International refereed conference proceedings and journals. Yan Pan is a Product Diagnostics EngineeringManager at GLOBALFOUNDRIES’ Fab 8 inMalta, N.Y. Hiswork covers scan diagnostics, layout analysis and statistical volume diagnosis, and electrical fault isolation for advanced technologies at Fab 8. In addition, he leads an effort at Fab 8 to develop volume data analysis infrastructure to identify and resolve systematic yield issues using fab process, test, yield, and product design data. Dr. Pan received his Ph.D. and M.S. degrees in computer engineering from Northwestern University, Evanston, Ill., in 2011 and 2010, respectively. He holds 3 patents and has published more than 20 papers from his work at Northwestern and GLOBALFOUNDRIES. ANADEF 2018 The 16th ANADEF Workshop will be held June 5 to 8, 2018, at Belambra Business Club, Seignosse-Hossegor (Landes), France. The conference addresses new issues related to the latest technological developments in electronic component failure analysis, presented through tutorials, plenary sessions, micro-workshops, as well as participation by equipment manufacturers and suppliers. ANADEF, a French nonprofit scientific society established in 2001, meets biennially to bring together industry experts and mechanism scientists concerned with the prevention, detection, and failure analysis of electronic components and assemblies. For more information, visit anadef.org . NOTEWORTHY NEWS