November_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 62 GUEST COLUMNISTS SPEEDING UP FAILURE ANALYSIS USING FAB AND DESIGN DATA Rao Desineni and Yan Pan, GLOBALFOUNDRIES rao.desineni@globalfoundries.com I dentifying, quantifying, and eliminating systematic defects is critical to the profitability of integrated circuit (IC)manufacturing. Ramping logic yield, as compared to that of SRAMarrays, is especially difficult due to the irregu- lar nature of the underlying physical design in advanced technologies. Double- and triple-patterning schemes, self-aligned via and metal-line strategies, and nonplanar transistor architectures such as FinFETs add extra com- plexity to yielding complex systems-on-chip (SOCs) that contain billions of logic gates. The increasing difficulty in profitably yielding SOCs, notwithstanding time-to-market and time-to-volume requirements on the foundries, has never been higher. As a result, rapid root-cause identifi- cation of logic failures is fundamental to the foundry and fabless business models. With billions of transistors integrated on a typical SOC in advanced technologies, the diversity of random logic design polygons and their topological neighbor- hoods is immense. Because only a tiny fraction of these topologies is captured in the scribe-line macros, all the design-process systematics causing logic fails cannot be captured by analyzing (e.g., failure analysis, or FA) only scribe-line structures. Systematic defect-identification techniques based on analyzing inline wafer-inspection data are limited to only those defects that can be detected using scanning electron microscopy, e-beam, or other optical inspectionmethods. Layout-aware scan diagnosis enables localization of failure locations withmuch higher precision,meaning a smaller portionof thephysical layout is provided as the target for FA. Most advanced layout- aware scan diagnosis software from reputed electronic design automation vendors further provide several extra FA guides, such as bounding boxes that highlight only the suspect layout polygons. This bounding box information can be fed into layout navigation tools such as Camelot to automatically drive FA tools towithin-die physical loca- tions. However, scandiagnosis resolutionhas always been challenging, meaning that the defect in the logic circuit cannot always be pinpointed to its physical location and the manufacturing process layer. Volume scan diagnosis techniques allow statistical analysis of layout-aware scan diagnosis results from multiple failing ICs, thereby mitigating the inherent diagnosis noise and improving the chances of success in identifying the root cause in FA. However, building a failure Pareto based on FA from multiple chips is not always the fastest option. The fab environment provides access to a large variety of data sources throughout the flowof wafer manufactur- ing process and test. From wafer manufacturing, these data types include, but are not limited to, lot logistics data (e.g., equipment, chamber, wafer slot position, q-time), inlinemeasurement data (e.g., critical dimensions, overlay for all important processing layers), inline defect-inspec- tion data, and electrical test data from inline scribe-line macros. From wafer and packaged modules test, data types include sort/bin test results (i.e., yield data), SRAM bitmap data, scan diagnosis data, statistical scoring results from volume diagnosis, and so on. It is possible, yet not always feasible, to store all these wafer-based data types in a common database inside the foundry. Somewhat orthogonal to wafer processing and test data “THERE IS A COMPELLING CASE FOR THE NEED FOR A FAST, FLEXIBLE, AND SCALABLE INFRASTRUCTURE THAT ENABLES BRINGING VARIOUS TYPES OF FAB MANUFACTURING PROCESS, TEST, AND DESIGN DATA TO ENABLE RAPID FA, LEADING TO FAST ROOT-CAUSE IDENTIFICATION.”