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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 40 opportunity to preserve the maximum functionality of the device. By using this approach, it is possible to not only image the device structures but also to interrogate by using a variety of probing techniques for the purpose of fault analysis or reverse engineering. Options include noncontact probing as well as electrical contacts using in situ manipulators and/or powering the device from outside the vacuum chamber. PLASMA FIB BACKSIDE DELAYERING Several proprietary gas chemistries are available for plasma FIB-SEM delayering. In general terms, the goal of the gas chemistry, in conjunction with appropriate ion beam energy and current density, is to homogenize the material removal of very heterogeneous structures consisting of a varying density of metal (i.e., copper and tungsten) and interlayer dielectric comprised of a type of porous silicon. To achieve this, the gas chemistry is typically designed to impede the rate of the faster milling components in order to balance the process. The gas chemistry may be modulated depending on the density of metal in the region of interest. The plasma FIB-SEM delayering process is relatively straightforward, consisting of a repeating sequence of steps that marry chemicophysical delayering with scan- ning electron imaging. Planar ion milling is performed while simultaneously exposing the regionof interest to the delayering chemistry. Following a user-defined period of exposure, the gas-assisted plasma FIBmilling is terminat- ed, and the system is prepared for electron imaging in the region of interest, using one or more imaging conditions (i.e., combining both low- and high-voltage imagingmon- tages at each delayering sequence). Imaging conditions include the desired optical parameters, such as acceler- ating voltage, beam current, field of view, pixel density, and the choice of detectors (secondary electrons, BSEs, etc.). The accelerating voltage governs the interaction volume and hence the depth fromwhich the information is extracted from the volume. Low voltage (i.e., 2 to 5 kV) produces the highest surface sensitivity and provides the best contrast todirectlyobserved p - and n -doping contrast at the transistor contact level. This information can in turn be used to identify NMOS and PMOS regions during the circuit-extraction process. High accelerating voltage (i.e., 30 kV) yields the greatest depth information and, when combined with BSE detection, allows one to peer one to three layers into the device structure to produce impel- ling pseudo-3-D perspective. Both types of information content are useful, and the choice of imaging condition(s) is driven by the aims of the analysis. If one is attempting tomaintain device functionality, such as in the case of an advanced circuit edit, it is critical tominimize the electron dose to avoid burning up the device. In other situations, the capability to use high voltage and moderate current density allows one to predict the density and location of subsequent layers not visible in low-voltage image data. This information may be useful as part of a multiresolu- tion imaging strategy to optimize the imaging montage schema. The imaging described here employed an auto- mated montage process that is user-defined. The user PLASMA FIB DEPROCESSING OF INTEGRATED CIRCUITS FROM THE BACKSIDE (continued from page 38) Fig. 5 An imagepair showing the initial ~800 × 800µmarea following removal of residual silicon fromthebackside of anOpteron processor. (a) 5 kV image acquired using an Everhart-Thornley-style secondary electron detector. Doping contrast is visible under these conditions. (b) 30 kV image at the same delayering step acquired with a backscatter detector. Under these imaging conditions, the interaction volume is greater, and the image signal is coming from a greater depth. (a) (b)