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edfas.org 31 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 2. V. Bertacco: “Post-Silicon Debugging for Multi-Core Designs,” Proc. Des. Autom. Conf., 2010, pp. 255-58. 3. M. Dehbashi and F. Görschwin: “Automated Post-Silicon Debugging of Design Bugs,” Proc. System, Software, SoC, and Silcon Debug Conf., 2011, pp. 67-71. 4. T.C. Luo, E. Leong, M.C.T. Chao, P.A. Fisher, and W.H. Chang: “Mask versus Schematic—An Enhanced Design-Verification Flow for First Silicon Success,” Proc. Int. Test Conf. (ITC), 2010, pp. 1-9. 5. K.L. Yeh, C.S. Chang, and J.C. Guo: “Layout-Dependent Effects on High Frequency Performance and Noise of Sub-40 nm Multi-Finger n -Channel and p -Channel MOSFETs,” Proc. Microwave Symp. Digest (MTT), 2012, pp. 1-3. 6. M. Bartley: “The Risks & Rewards of Early Tapeout,” EETimes, 2014, eetimes.com/author.asp?section_id=36&doc_id=1323158. 7. C. Edward: “Early Tape-Out: Smart Verification or Expensive Mistake?” Tech Des. Forum, 2014, techdesignforums.com/practice/ technique/tape-out-verification-shift-left. 8. J. Keshava, N. Hakim, and C. Prudvi: “Post-Silicon Validation Challenges: How EDA and Academia Can Help,” Proc. Des. Autom. Conf., 2010, pp. 3-7. 9. D. Lin, E. Singh, C. Barrett, and S. Mitra: “A Structured Approach to Post-Silicon Validation and Debug Using Symbolic Quick Error Detection,” Proc. Int. Test Conf. (ITC), 2015, pp. 1-10. 10. F. Farahmandi, R. Morad, A. Ziv, Z. Nevo, andP. Mishra: “Cost-Effective Analysis of Post-Silicon Functional Coverage Events,” Proc. Des., Autom., Test Eur. Conf. Exhib., 2017, pp. 392-97. 11. D. Gizopoulos: Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006. 12. B. EklowandB. Bennetts: “NewTechniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG),” Proc. Int. Test Symp., 2006, pp. 253-54. 13. B. Vermeulen, T. Waayers, and S.K. Goel: “Core-Based Scan Architecture for Silicon Debug,” Proc. Int. Test Conf. (ITC), 2002, pp. 638-47. 14. X. Liu and X. Qiang: Trace-Based Post-Silicon Validation for VLSI Circuits, Springer, 2014. 15. D. Bockelman et al.: “Multi-Point Probing on 65 nm Silicon Technology Using Static IREM-BasedMethodology,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2005, pp. 40-45. 16. S.Y. Ng et al.: “Laser Voltage Imaging: A New Perspective of Laser Voltage Probing,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2010, pp. 5-13. 17. M.R. Bruce, L.K. Ross, and C.M. Chua: “On Die Logic Analysis through the Backside,” Proc. Int. Phys. Fail. Anal. Integr. Circuits (IPFA), 2014, pp. 366-69. 18. W.Lua,G.Ranganathan,V.K.Ravikumar,andA.Phoa:“Combinational Logic Analysis Case Studies Using Laser Voltage Probing,” Proc. Int. Phys. Fail. Anal. Integr. Circuits (IPFA), 2016, pp. 51-54. 19. B. Niu, G.M.E. Khoo, Y.C.S. Chen, F. Chapman, D. Bockelman, and T. Tong: “Laser Logic State Imaging,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2014, pp. 65-72. 20. S.H. Goh et al.: “Evolution of Wafer Level Tester-Based Diagnostic System: More than just a Dynamic Electrical Fault Isolation Tool,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2013, pp. 587-93. 21. S.H. Goh et al.: “Effectiveness of FrequencyMapping on 28 nmDevice Broken ScanChain Failures,” Rev. Sci. Instrum., 2012, 83 (2), p. 023702. 22. S.H. Goh et al.: “Wafer-Level Fault Isolation Approach to Debug Integrated Circuits JTAG Failures,” Proc. Int. Phys. Fail. Anal. Integr. Circuits (IPFA), 2014, pp. 30-34. 23. B.L. Yeoh, S.H. Goh, et al.: “Debugging MBIST Hard Fails without Bitmapping,” Proc. Int. Phys. Fail. Anal. Integr. Circuits (IPFA), 2015, pp. 138-43. 24. “Reverse Engineering Software,” Chipworks, chipworks.com/en/ technical-competitive-analysis/resources/ reverse-engineering- software, accessed May 2014. 25. Degate, degate.org/documentation. 26. M. El Massad, S. Garg, and M.V. Tripunitara: “Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes,” Proc. Network Distrib. Syst. Security (NDSS) Symp., 2015. 27. K.Y. Kenneth and C.N. Berglund: Automated System for Extracting Design and Layout Information from an Integrated Circuit, U.S. Patent 5,086,477, 1992. 28. “Calibre xRCParasitic Extraction,” Datasheet, Mentor Graphics,2004. 29. QRC, Extraction User Manual, Version 11, Cadence, 2015, p. 1. 30. “Extraction Techniques for High-Performance, High-Capacity Simulation,” Synopsys, 2009. 31. Dolphin Integration, “Analog & Mixed Signal IC Debug: A High Precision ADC Application,” 2017 Design and Reuse, https://www. design-reuse.com/articles/19575/analogmixed-signal-ic-debug. html. ABOUT THE AUTHORS Edy Susanto received his M.Sc. degree in IC design from Nanyang Technological University. He joined Philips Semiconductors, later NXP Semiconductors, and ST-Ericsson as an analog IC design engineer focusing on universal serial bus transceiver design and later communication combo chips with FM radio, Bluetooth, wireless local area network, and near-field communication applications. He joined GLOBALFOUNDRIES in 2013, where he is responsible for process integration and has sub- sequently ventured into product diagnostics for CMOS, MEMS, and silicon photonics products. Edy has vast experience in the semiconductor industry, including design, verification, validation, process, electrical test, process control modules, and product testing. He takes great interest in leveraging his immense experience to enhance yield ramping in the foundry. Szu Huat Goh received his B.Eng. and Ph.D. degrees in electrical and computer engineering from the National University of Singapore. Dr. Goh is currently with GLOBALFOUNDRIES’ Product, Test, and Failure Analysis Division in Singapore, where he leads a team responsible for product failure diagnostics and advanced methodologies to accelerate yield ramp. His main focus is the develop- ment of dynamic fault isolation techniques, wafer-level fault isolation methods, and leveraging cross-functional domain knowledge of design, test, and failure analysis to enhance yield learning. (continued on page 34)

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