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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 30 of resistance of the poly resistors. A secondary analysis of the layout reveals that the lower half of the potential divider has a distinctive routing compared to the upper half, which is a straightforward serpentine of discrete resistors in series. The lower half has a combination of resistors connected in series and in parallel. The SDL signals identify the highest-sensitivity region to be on the serial resistors at the lower-half portion of the divider. It is recommended that the routing be consistent on both halves of the divider tomitigate the process sensitivity for better parametric matching. PEX EXTRACTION CHALLENGES Although it may seem convenient to generate and study the schematic of the CUD using PEX as compared tomanual translation, they are complementary in nature; there are cases where PEX is not effective, as substanti- ated by Fig. 13. Before any PEX execution, the chip layout is clipped to a smaller region that encompasses the CUD. It includes all process layers within the region of interest, thus leading to multiple transistors that are not directly relevant. An example is dummy transistors. Figure 13(a) shows a cluttered, flattenedPEX schematic that cannot be easily interpreted for a reasonable analysis. Figure 13(b) shows the schematic following a post-dummy transistors filtering procedure. Although it may appear manageable, the opportune outcome is to achieve a schematicwith not more than three stages fromthe suspected failing location to minimize the number of intranodes as stimulus and observation points, to facilitate testbench simulations. More work is required to accomplish this, and manual trace is still favored in some situations. CONCLUSION There exists a common goal between design houses and foundries: to constantly strive for faster time-to- production of a new product. To accomplish this, first- silicon success or timely issue resolution is paramount. Foundries have an important role to play above their core competence in addressing potential process con- cerns. This article reinforces the possibility of foundries to engage in preliminary postsilicon validation activities instead of sole reliance on design houses, specifically on design bugs or design-related marginalities failures that are encountered on first silicon. Methods and examples have been presented to demonstrate how foundries can effectively contribute as an added resource to debug such failures. Although the scope is limited to elementary circuitries, the impact exists. In this way, design houses can zero in on more complicated design issues. It is time to revamp the collaboration between design house and foundry. This is just the beginning. REFERENCES 1. N. Hakim: “Introduction to Post-Silicon Validation,” 2010, eecs.wsu. edu/~rliu1/files/PostSiValidation.pdf. Fig. 13 PEX netlist based on a random clipped layout (a) in the raw form and (b) after filtering dummy transistors (a) (b)