November_EDFA_Digital

edfas.org 29 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 Fig. 11 (a) SDL signal overlay image and (b) corresponding layout indicating five thermally sensitive sites. (c) Testbenchmodel of CUD (a) (b) (c) Fig. 12 Testbench simulation on CUD when A = 0, B = 1, and C = 1, as shown by the case in Fig. 10(b), the driving net is found to be stuck at midrail bias. The outcome is a leakage in Inv 2, which explains the photon emission micrograph observation. The issue was identified and a process fix was implemented to resolve the failure. Although all nets in a typical combinational logic circuit should be clearly defined, this is a classic example of a design bug escape in presilicon validation. This is a common phenomenon, especially in complex mixed-signal designs. [31] LAYOUT-DESIGN-RELATED PROCESS SENSITIVITY Process transfers acrosswafer fabricationplants (fabs) within a foundry are common to optimize capacity. A case of a consistent higher pin voltage output from a silicon- on-chip from the receiving fab, as shown in Fig. 2(b), is discussed. The test response (voltage readout) presents a negative sensitivity to thermal stimulus. Soft defect localization (SDL) is chosen to isolate the critical circuit- ries. Figure 11(a) shows the SDL signal overlay image. Five signal spots were obtained, and a layout analysis found themto be related to some contacts of poly resistor chains (Fig. 11b). PEX extraction was performed to derive the schematics of the CUD, and the testbench model is shown in Fig. 11(c). The voltage observation pin as well as the signal locations (area of interest) are indicated. The circuit is a simple potential divider. Figure 12 shows the testbench simulation result. The lowering of the voltage output can be explained by the temperature coefficient