November_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 28 2 is not recommended. The inputs A, B, and C to the com- binational logic involved in the CUD were identified and a testbench model was created. In the circuit simulation, various combinations to the inputs were applied, and the crossover current of the three inverters was monitored together with the state of the output driving net from Inv 1. The results of two scenarios are presented in Fig. 10. Figure 10(a) shows that when A = 0, B = 1, and C = 0, the driving net to Inv 2 is defined as 0, and the drain current is found to be negligible in all three inverters. However, Fig. 9 Testbench model of CUD. Labels A, B, and C are inputs. Fig. 10 Drain current of inverters 1 to 3 under input state of (a) A = 0, B = 1, C = 0 and (b) A = 0, B = 1, C = 1 circuitry.Next, theschematicwasderivedusingthemanual trace method before circuit analysis ensued. Figure 9 shows a schematic of the circuit under debug (CUD) fol- lowing guidance from the abnormal photon emissions, whichwere observed on inverter 2 (Inv 2). Inverter 1 (Inv 1) is the preceding instance, while Inverter 3 (Inv 3) is driven by Inv 2. Consider the case of a defect in Inv 1 leading to saturation in Inv 2; intuitively, the input to Inv 3 will be floating, and emissions should be observed aswell. Based on experience, direct physical failure analysis on Inv 1 and (a) (b)