November_EDFA_Digital

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 26 Fig. 4 Block diagram of a standard Calibre PEX flow Fig. 5 Modified Calibre PEX flowchart Fig. 6 (a) Layout, (b) extracted flattened transistor netlist, and (c) hierarchical netlist representation of a generic decoder (a) (b) (c) PRODUCT CIRCUIT VALIDATION AND FAILURE DEBUG (continued from page 24) (a) (b) (c) scan design flip-flop. The corresponding schematic that is derived from manual tracing is shown in Fig. 3(b). A circuit analysis can be performed to shed insight on the bias conditions of the operatingmodes and the expected performance of the scan cells.