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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 24 such as multiple emission hotspots that are related by multiple connecting nets and parametric-related issues (Fig. 2a and b, respectively), circuit analysis is necessary. CIRCUIT ANALYSIS METHODS Circuit analysis for failure debug is distinctly different from IC reverse engineering that is commonly performed to detect IP infringements or examine chip security. Reverse engineering involves the use of physical methods to remove the materials layer by layer and acquire high- resolution images at each layer for reconstruction of the layout of the entire IP, or even the chip design, and thereafter generate a schematic. Companies and soft- ware tools such as Chipworks and Degate have been well established for this purpose. [24-27] Circuit analysis in this article’s context refers to examining partial and a much smaller network of circuit components, usually involving one to two levels of fan-in/out net traces that connect the suspected failing instance. In general, this can be accom- plished in two ways by the foundry. MANUAL TRACE The smallest building block to construct a circuit schematic is a basic transistor. From a layout, it can be extractedbasedon the overlapof polysilicon anddiffusion areas. Subsequently, the connecting nets can be traced to mapout the relevant netlist. Although thismanual process is tedious and time-consuming, there is no sophistication in the knowledge that is required to accomplish this task. It is fundamental to all semiconductor engineers. Figure 3(a) represents the layout of a typical level-sensitive Fig. 2 (a) Photon emission micrograph showing hotspots not related by a single trace. (b) Parametric test response discrepancies between processed silicon from two foundries Fig. 3 (a) Layout representation and (b) corresponding schematic frommanual trace of a typical level-sensitive scan flop (b) (a) (b) (a) (continued on page 26)