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edfas.org 23 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 ROLE OF SEMICONDUCTOR FOUNDRY IN FIRST-SILICON VALIDATION AND FAILURE DEBUG A semiconductor foundry is strongly motivated by revenue generation to ensure that a design tapeout releases to production from technology development in the shortest possible time. However, besides the advances in design-for-manufacturing efforts to increase the odds of first-silicon success, postsilicon validation and design debug, as a last gate, is usually noncollaborative in nature between design centers and foundries. By tradition, the latter are expected to focus only on process fixes for the reason mentioned in the previous section, while the former assume the responsibilities for design-related matters. Moving forward, the clear demarcation between process or design bugs is becomingmore obscured due to the tighteningmargins in both aspects, and it is time for a paradigm shift for both facilities to step out of their silos and start working together tomeet the aggressive sched- ules for early product time-to-market. Although foundries are not the best candidates to partake in silicon validation entirely, the truth is they can help to some extent, espe- cially with designmarginalities, because they often have expertise and toolsets not available to design houses. One of the most useful tools for identifying design marginalities in ICs is the laser scanning microscope. In most modern foundries, tester-based scanning laser microscope diagnostic tools are readily available for device electrical fault analysis. Automatic test equipment docks onto the diagnostic tool to power up the device while failure analysis is performed concurrently. [20] In this way, functional issues can be interrogated. [21-23] Although the specifications of these tools are capable to apply for designdebug, they usually are not utilized for this purpose due to the lack of sufficient design knowledge, such as the expected states at suspected problematic internal nodes. In fact, design centers could leverage this untapped resource for parallel effort in the characterization and root-cause understanding of test failures. This is the first area for collaboration. The second opportunity for a foundry to contribute is related to debug on the design schematic to postulate the failure mechanism and to guide subsequent failure analysis steps, after the successful localization of sus- pected problematic circuitries. Often, design centers are relied upon extensively to accomplish this task. Actually, some basic preliminary analysis can be performed by a foundry to shorten the learning cycle. Figure 1 illustrates two examples of abnormal emission hotspot observa- tions after fault isolation. In both cases, a single failing net connecting the signal locations is able to explain the root cause of the failure. In such scenarios, simple layout analyses suffice. For more complicated failure modes, Fig. 1 Layout trace of suspected failing net connecting (a) single emission hotspot and (b) multiple emission hotspots (b) (a)