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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 22 PRODUCT CIRCUIT VALIDATION AND FAILURE DEBUG: A SEMICONDUCTOR FOUNDRY CAN HELP Edy Susanto, S.H. Goh, Edmund C. Manlangit, and Jeffrey Lam GLOBALFOUNDRIES, Technology Development, Product, Test, and Failure Analysis, Singapore szuhuat.goh@globalfoundries.com EDFAAO (2017) 4:22-34 1537-0755/$19.00 ©ASM International ® INTRODUCTION Before a product enters mass production, a series of design validation and debugging procedures precede as part of the qualification process. Generally, they are broadly classified into simulation-based presilicon valida- tion and postsilicon validation using prototype samples tested under the actual system environment. Despite the painstaking efforts that employ varied simulators and emulators to ensure a clean design tapeout prior to manufacturing, bugs that escape presilicon verification are on the rise [1-3] due to increasing design complexity in modern chips and a widening discrepancy between simulation and actual functional performance as process technologies advance. [4,5] Ingeneral, there are two types of designbugs. Logic or functional bugs are causedby design errors or insufficient validation coverage. Electrical or circuit bugs that manifest under certain operating condi- tions can be caused by design marginalities and process variations. As a statistical reference, it was reported that approximately 2 and 10% of logic and circuit bugs, respectively, were discovered and fixed at postsilicon validation. [1] This situation is expected to be worsened by recent rising trends of third-party intellectual property (IP) modules integration, increasing clock speeds, narrowing design windows due to tightened design rules, and more aggressive production schedules. In addition, there have also been ongoing discussions to enter tapeout early and interrogate the bugs on actual silicon; the justification is a potential shortening of the entire design verification process. [6,7] This explains why postsilicon validation is gaining more traction and why increased efforts are criti- cal to ensure no escapes into production after this final stage of verification. [8-10] Postsilicon validation encompasses evaluating the functional response of the prototype units per se and their interactions at a system-level platform. Unlike presilicon validation, the tests are usually performed at speed, offering faster lead time. However, this advantage comes at a trade-off of limited observability and intensi- fied debug complexity, because internal nodes cannot be easily assessed and modified on silicon. To achieve debugging, design for testability (DFT) elements such as the IEEE Standard 1149.1 test access port (JTAG), [11] IEEE Standard1687 (IJTAG), [12] and scan-based architecture are leveraged to capture and shift data out of circuit internal nodes. [13] For elusive bugs that onlymanifest under certain operational time lapse or conditions, a more effective technique is employed that traces internal circuit signals continuously during testing. [14] Although these techniques are well established and efficient, failures in the field, especially related to design marginalities, are inevitable due to shortcomings in test coverage or advanced fault models. Debugging these test escape fails that occur sporadically is challenging but also part of the postsilicon validation process. Over the last decade, the tester-based laser scanning optical microscope tool has been increas- ingly adopted as an added approach. It is mainly used to debug internal circuit logic and speedpaths at large. Some techniques related to such applications are waveform probing of internal nodes [15-18] and logic statemapping. [19] Fundamentally, be it software- or hardware-based approaches to postsilicon failure debug, an in-depth knowledge of the DFT or design for debug circuitries in the integrated circuit (IC) is requisite. Therefore, it is natural that such activities can only be conducted by design centers and not IC contract manufacturers (foundry). Product time-to-mass-production thus relies solely on the available resources within the design centers to fix the errors.

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