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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 14 the depletion layer. The depletion-layer geometry, in turn, depends on the tip-sampledirect current or low-frequency voltage and on the doping level of the semiconductor. Analytical solutions exist for one-dimensional geom- etries, and these can be used to model the results from macroscopic parallel-plate metal oxide semiconductor (MOS) structures. Figure 3 shows the classic parallel-plate model for describing a MOS device. A lumped-element approximation for an sMIM tip on an oxide-coated semi- conductor andexpressions fromthedeltadepletionmodel for depletion-layer thickness [17] are shown in Fig. 3. Because depletion-layer geometry has a strong impact on sMIMsignals andbecause thedepletion-layer geometry varies with tip-sample voltage and with doping, varying the tip-sample voltage is a way to characterize semi- conductor materials and devices, particularly the local Fig. 3 (a) Schematic of the classical MOS device configuration with the sMIM probe contacting a sample surface modeled as two series capacitors. The equations describe the relationship of the capacitance (and therefore the sMIM)measurement on the depletion-layer thickness and doping concentration. (b) Numerically generated capacitance-voltage curves from the parallel-plate model illustrate sMIM’s sensitivity to semiconductor doping level. Fig. 4 (a-d) Finite-element model (FEM) predictions of the majority carrier hole density in the presence of marked biases on an sMIM probe for the marked p -type doping densities in silicon. Many more such simulations led to (e) FEM predictions of C-V curves, with the dopings specified by the legend. (f) Calibration of the probe tip’s capacitance over the various doped samples as a function of their doping density (a) (b) (a) (b) (c) (d) (e) (f)