A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2023 | VOLUME 25 | ISSUE 1 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org MAKING CONNECTIONS: CHALLENGES AND OPPORTUNITIES FOR IN SITU TEM BIASING THINNING AND POLISHING HIGHLY WARPED DIE: PART II AN INVENTOR’S TALE OF FIB IN SITU LIFT-OUT sMIM: OVERVIEW AND LOW TEMPERATURE OPERATION 4 16 9 20
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2023 | VOLUME 25 | ISSUE 1 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org MAKING CONNECTIONS: CHALLENGES AND OPPORTUNITIES FOR IN SITU TEM BIASING THINNING AND POLISHING HIGHLY WARPED DIE: PART II AN INVENTOR’S TALE OF FIB IN SITU LIFT-OUT sMIM: OVERVIEW AND LOW TEMPERATURE OPERATION 4 16 9 20
edfas.org 1 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 DEPARTMENTS Scanning Microwave Impedance Microscopy: Overview and Low Temperature Operation Nicholas Antoniou Scanning microwave impedance microscopy is a nearfield technique using microwaves to probe the electrical properties of materials with nanoscale lateral resolution. Author Guidelines Author guidelines and a sample article are available at edfas.org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 9 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2023 | VOLUME 25 | ISSUE 1 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS 2 GUEST EDITORIAL Joe Caroselli, Renee Parente, and Tom Schamp 34 PANEL & USER GROUP SUMMARY 41 2022 EDFAS AWARD WINNERS 42 2023 EDFAS AWARDS 43 CALL FOR NOMINATIONS James Demarest 44 BOARD OF DIRECTORS NEWS Chris Richardson 45 DIRECTORY OF FA PROVIDERS Rosalinda Ring 47 TRAINING CALENDAR Rosalinda Ring 49 LITERATURE REVIEW Michael R. Bruce 51 PRODUCT NEWS Ted Kolasa 54 GUEST COLUMN Yan Li 56 ADVERTISERS INDEX Processes for Thinning and Polishing Highly Warped Die to a Nearly Consistent Thickness: Part II Kirk A. Martin The processes and considerations for locally thinning an area of interest to the desired remaining silicon thickness are described. 16 For the digital edition, log in to edfas.org, click on the “News/Magazines” tab, and select “EDFA Magazine.” Making Connections: Challenges and Opportunities for In Situ TEM Biasing William A. Hubbard This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples fromelectronic components, as well as strategies to mitigate these issues. 9 4 Transforming an Industry: An Inventor’s Tale of FIB In Situ Lift-Out Cheryl Hartfield This is the story of how the mainstream Omniprobe FIB lift-out solutionwas invented and delivered to themarket. 20 ABOUT THE COVER “Sparky the Cap.” Blown ceramic stacked cap microsection. Sparky was the “face” of this failure. Photo by Stephen Fasolino, Raytheon Technologies, First Place Winner in Color Images, 2022 EDFAS Photo Contest. 16 20 ISTFA 2022 Highlights A recap of the ISTFA 2022 event includes General Chair Zhigang Song’s wrap-up as well as a list of the winning ISTFA papers and posters. 30
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Mary Anne Fleming Director, Journals, Magazines & Digital Media Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Innovation Systems Rosalinda M. Ring Thermo Fisher Scientific Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright©2023by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization tophotocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registeredwith theCopyright ClearanceCenter (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly toCCC, 222 RosewoodDrive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. The Electronic Device Failure Analysis Society (EDFAS) is an affiliate society within ASM International (ASM) with several unique attributes. EDFAS has its own magazine, user groups that meet during their annual conference, the International Symposiumfor Test andFailureAnalysis (ISTFA)meeting, and local chapters. Historically, the EDFAS chapters have been theGoldenGateChapter based in theCaliforniaBay Area and the Lonestar Chapter based in the Dallas area. Over time, the significant growth of the semiconductor industry in the Austinmetroplex suggested to the EDFAS Board that the Lonestar Chapter may thrive if relocated. Thus in 2019, the authors of this article initiated the process of relocating the Texas-based Lonestar Chapter to help it reach a broader base. Plans weremade to shift the chapter to the Austinmetroplex and organize meetings basedaround the goals of networking andproviding benefits from the EDFASmembership beyond the ISTFA annual meeting. By February of 2020, the team was set to send out invitations kicking off the relocated Lonestar Chapter. However, as we all know, in early 2020, the state of the world forced all plans for in-person gatherings to go on hold. Instead, the chapter began hosting virtual meetings with guest speakers from academia and industry, which importantly initiated the regular interaction of the Texas EDFAS community. On October 4, 2022, the EDFAS Lonestar Chapter gathered in person in Austin, Texas for a social event attended by approximately 18 people from various companies. All attendees shared a connection to the electronic device failure analysis community and this great event facilitated the connection of many that were to see each other again at ISTFA in Pasadena, Calif. a few weeks later. The fundamental goal of the local chapter is now being recognized. Both members and prospective members of EDFAS and ASM are putting faces to names, meeting those who might offer technical insights, or who might be a future hiring manager. Interns mingled with experienced professionals, emerging professionals met with vendors, and non-members were seeing a benefit of joining EDFAS and ASM. FEBRUARY 2023 | VOLUME 25 | ISSUE 1 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL THE REVITALIZATION OF THE EDFAS LONESTAR CHAPTER Joe Caroselli, AMD joseph.caroselli@amd.com Renee Parente, AMD renee.parente@amd.com Tom Schamp, Materials Analytical Services tschamp@mastest.com edfas.org Caroselli (continued on page 56) Parente Schamp
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 4 EDFAAO (2023) 1:4-8 1537-0755/$19.00 ©ASM International® MAKING CONNECTIONS: CHALLENGES AND OPPORTUNITIES FOR IN SITU TEM BIASING William A. Hubbard NanoElectronic Imaging, Riverside, California bhubbard@nanoelectronicimaging.com INTRODUCTION The transmission electron microscope (TEM) is an essential tool for high-resolution imaging of micro and nano-electronic systems for basic research, fabrication quality control, and failure analysis. Despite the ubiquity of TEM, in situ biasing experiments involving electronic devices are markedly rare, with most examples found in academic studies. This is not for lack of interest, as the ability tooperateor inducedefects indeviceswhileobserving the resulting nanoscale dynamics would undoubtedly provide valuable information. Themain barrier to routine biasing of electronic devices in the TEM is the difficulty in producing electrically contacted samples that are both TEMcompatible and electronically viable. This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues. It will also describe the potential benefits of developing techniques for high-throughput sample fabrication that preserves the electronic behavior of parent devices. Scanning TEM electron beam-induced current (STEMEBIC) is presentedas botha tool uniquely capableof assessing progress in achieving these fabrication goals as well as a complement to standardTEM imaging, producing contrast directly related to a device’s electronic structure, including local conductivity. SAMPLE PREPARATION STRATEGIES AND CHALLENGES The most hindering constraint on samples for TEM imaging is the requirement of electron transparency— that samples be thin (~100 nm or less). Broadly, there are two routes for preparing electronic device TEM samples: extracting a thin cross section (or lamella) from a larger device, and micro-fabricating a device from the ground up to be thin but functional. Cross sectioning, most commonly using a focused ion beam (FIB), enables studying samples from “real” components (i.e., devices that may be deployed in electronic systems), which is particularly appealing for studying failure and reliability. However, surface damage and contamination from the FIB milling process typically degrades the electronic structure of devices. The latter (micro-fabrication) approach enables precise control of device features, straightforward electrical connection, and entirely avoids the damage and contamination associated with FIB preparation. Such devices are well-suited to serve as model systems, where dynamics can be observed in a device that is analogous to a deployed device of interest. Such observations can Fig. 1 SEM images of a Si-based lift-out biasing chip. The Si-based chip supports a thin membrane and Pt electrodes that are patterned up to a trench etched through the membrane which is positioned at the edge of the chip. The lower image is tilted 45 degrees in the direction of the trench.
edfas.org 5 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 provide insight into device physics but may not represent the truebehavior of anoff-the-shelf component, and these devices are therefore more appropriate to basic research purposes. This articlewill focus onFIBsamplepreparation, as it is a standardized process, to the point of automation, and therefore presents themost direct route to routine in situ TEM characterization within existing workflows. FIB-prepared TEM samples are typically mounted to TEM lift-out grids, or semicircular conducting discs with protruding posts on which lamellae can be mounted. Samples mounted on these grids may be used for biasing experiments when loaded into a biasing sample holder equipped with a moveable probe. With the grid serving as ground, bias can be applied via the probe to several thinned devices on a single grid. However, making this mechanical connection in situ produces irregular strain and electric fields that may result in unrealistic device function, and the single probe only allows for a single measurement or applied stimulus at a time. Amuchmore common style of biasing holder includes a chip carrier on which Si-based substrates can be loaded and through which multiple electrical connections canbemade simultaneously. TheseMEMS-based biasing holders are compatible with an array of chips that can be equipped with heaters, platforms for mounting cross sections, as well as more complicated micro-fabricated devices. There are a variety of commercially available and custom-made substrates formounting crosssection samples for in situ biasing. The substrate shown inFig. 1 consists of aSi chiponwhicha thin membrane has been etched via anisotropic KOH etching.[1,2] Large pads are patterned tomatch the mounting/connectionmechanismof the holder, and thinner leads protruding from these pads extenddown to the thinmembrane at the edge of the chip. Here a trench has been plasma-etched in the membrane over which a cross section can be suspended. The standard approach for FIB-preparation of bias-enabled TEM samples, shown in Fig. 2, begins with the milling and extraction of a (relatively thick) cross section from the macroscopic component of interest. The section is then mounted to the Si-based biasing chip with electrical leads deposited, via beam-bombardment of metal-organic gas injected near the sample, to connect to the patterned chip electrodes. Portions of the device must then be milled to electrically isolate device layers. For example, the photodiode in Fig. 2 is milled such that one electrode connects to the substrate and the other to the device’s top electrode. Without this rudimentary circuit edit, the electrode and substrate would be shorted, and electronhole pairs produced in the active device region would recombine. For samples where a bias is to be applied, milling can maintain the fidelity of nominally insulated device regions. Following the selective milling step, the suspended region of the device must be thinned to electron transparency, as in standard FIB sample production. The final step is a low-energy, low-current cleaning of the sample surface. This cleaning reduces surface damage, implantation, and heating. The final surface cleaning is perhaps the most critical step in production of viable TEM biasing samples that behave similar to their parent devices. Optimizing this cleaning procedure is therefore the chief area of improvement necessary for routine implementation of in situ biasing techniques in the TEM. Milling and metal deposition can spray material several micrometers from Fig. 2 FIB preparation of a Si photodiode. (a) Photograph of the photodiode before FIB milling. (b) SEM image of a (relatively thick) cross section FIB-milled at the edge of photodiode’s top electrode, in the region indicated by the small red box on the left side of (a). (c) Cross sectionmounted to the Si-based chip shown in Fig. 1. Metal electrodes are written to either side of the lamella via metal-organic FIB deposition. Sections of the lamella are milled away to electrically isolate regions of the device: the left electrode is connected to the substrate and the right electrode to the top electrode. A section in themiddle of the device is thinned to ~100 nm. (d) Image of the final device, with the region imaged in Fig. 3 indicated by the yellow box.
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 6 the incident ionbeamandonto the lamella surface. During the thinning process, excess beam current can cause heating that results in precipitation of any volatile elements present (e.g., indium, gallium) to the surface, and excess beam energy can implant beam ions 10s of nanometers into the sample surface. Fortunately, techniques developed for atomic resolution imaging of FIB-prepared samples include steps to mitigate these effects,[3] though it does not seem likely that implantation can be avoided entirely. The most commonly used ion for FIB is Ga+, and surface implantationcanproducea layer of conductingGa, however plasma FIB (PFIB) systems, where the beamconsists of inert Xe+ ions, are becomingmore common. There are also a number of other elements (e.g., He, N, O, Ar) currently used in ion beams, each with varying contributions to implantation,[4] damage, and surface chemistry, making the ionparameter space apotentially fruitful place to explore in pursuit of higher quality sample preparation. For optimal sample thickness and uniformity there are a number of established procedures (e.g., tilting, rocking, post-FIB ionmilling) that may also improve the electronic quality of samples. While there is still a significant amount of development necessary to standardize processing for bias-enabled TEM samples, several successful samples have been reported recently.[5-10] IN SITU BIASING AND STEM EBIC In situ biasing allows for electronic and thermal manipulation of devices while imaging in the TEM, potentially revealing nanoscale device characteristics that are otherwise only studied via electrical testing or modeling. A sample can be electrically or thermally stressed while imaging, allowing live observation of the resulting nanoscale defect formation and real-time correlationwith electronic signatures of failure. The interplay between structure and function in contemporary components can be studied directly, providing rational directions for improvements in future iterations. The operatingmechanisms behind incompletely understood, next-generation components may be studied directly, expediting their development and mainstream implementation. In many cases in situ operation of devices may yield actionable information, but the ability to operate devices in situ does not guarantee that bias-induced changes will bedetectablewithstandardTEMimaging techniques. For a given device geometry under bias, somematerial systems may produce physical changes that generate obvious TEM contrast while others generate no TEM contrast despite electrical measurements confirming their operation (see, for example, references 11 and 12). This is largely due to the nature of TEM imaging itself. TEM’s scattering-based contrast only provides information related to the physical structure of a sample—the number and type of atoms and their arrangement. TEMmay be blind to electronic signals in samples, which are often the dynamics of interest for devices. The function and failure of devices often originate with changes to electronic structure that onlymanifest as a detectable physical changewhen such changes become pathological and produce defects. To take full advantage of clean, electrically connected TEM samples, TEM-based imaging techniquesmust be employed that directly probe the electronic structure of devices. One such technique is STEM EBIC imaging. EBIC is the measurement of current generated in a sample as it is irradiated by an electron beam, with EBIC images formed by measuring the current pixel-by-pixel at each beam position. The most commonly used mode of current generation, the separation of beam-induced electron-hole pairs by a local electric field, is referred to as the “standard” EBIC mode. Standard EBIC has been in use since the 1960s[13] and is routinely performed in an SEM, alongwith associated nanoprobing techniques such as electron beam absorbed current (EBAC) and electron beam-induced resistance change (EBIRCH).[14-16] Standard EBIC can also be measured in the TEM (Fig. 3), however it often yields images similar towhat can be obtained in the SEM; the large interaction volume associated with standard EBIC often negates the superior resolution of TEM. Recently,[1] an additional EBIC mode has been demonstrated in the TEM, called secondary electron emission EBIC (SEEBIC), which measures the holes left behind by emission of secondary electrons. SEEBIC is typically a much smaller signal than standard EBIC for a given beam condition and therefore requires much more sensitive current measurements for detection, often by several orders of magnitude. Owing to the higher beamenergy in TEMand the electron transparency of samples, the SEEBIC interaction volume is very small, enabling the measurement of SEEBIC with atomic resolution.[17] A unique property of SEEBIC is the ability to generate high resolution resistance contrast images, as the holes preferentially reach ground either via the EBIC amplifier or another path to ground depending on the relative resistance of the two paths.[12,18] SEEBIC resistance mapping can be performed while biasing, producing, for example, obvious contrast related to local conductivity changes in the early stages of dielectric breakdown.[12] The samplepreparationconsiderations for TEMbiasing samples are in alignment with those for obtaining highquality STEMEBIC: samplesmust be electron transparent,
edfas.org 7 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 electrically connected, anddevoidof confoundingdamage and contamination. Even in FIB-prepared samples where surface leakage dominates transport under bias, the STEM EBIC signal can still providedetailed informationabout the local electronic structure.[18] For example, the photodiode in Fig. 3 generates strong EBIC contrast while exhibiting 1000 times more leakage than its parent device despite having a 1 million times smaller active device area. STEM EBIC can also play a role in the development of FIB-based biasing sample preparation, providing a quantitative assessment of samples’ electronic structure, including straightforward visualization of device connectivity and isolation across nominally insulating regions.[19] CONCLUSION With optimization of the sample preparation procedure, in situ biasing and STEM EBIC measurements can be implemented as routine methodologies within existing characterization workflows. The feasibility of reliably producing samples from a given device depends largely on the particulars of the device itself. Samples extracted from components with volatile constituent materials or that require isolated electrical connections to electrodes in very close proximity are particularly difficult cases. The vast array of materials and device architectures further complicates the prospect of achieving standardized, automated processing for bias-enabled TEM samples. Reliable processing may be achievable but will likely require the combined efforts of a number of research groups. In particular, collaboration is encouraged across the failure analysis and electronics manufacturing communities where there exists substantial expertise in high-throughput, high-quality TEM sample preparation and nanoscale circuit editing. ACKNOWLEDGMENTS This material is based upon work supported by the Defense Microelectronic Activity under Contract No. HQ072721C0002. REFERENCES 1. W.A. Hubbard, et al.: “STEM Imaging with Beam-Induced Hole and Secondary Electron Currents,” Phys. Rev. Appl., 10(4), p. 044066, Oct. 2018, doi: 10.1103/PhysRevApplied.10.044066. 2. M. Mecklenburg, et al.: “Fabrication of a Lift-Out Grid with Electrical Contacts for Focused Ion Beam Preparation of Lamella for In Situ Transmission Electron Microscopy,” Microsc. Microanal., 19(S2), p. 458–459, Aug. 2013, doi: 10.1017/S1431927613004285. 3. M. Schaffer, B. Schaffer, and Q. Ramasse: “Sample Preparation for Atomic-resolution STEM at Low Voltages by FIB,” Ultramicroscopy, Vol. 114, p. 62–71, Mar. 2012, doi: 10.1016/j.ultramic.2012.01.005. 4. K. Eder, et al.: “A Multi-ion Plasma FIB Study: Determining Ion Implantation Depths of Xe, N, O, and Ar in Tungsten via Atom Probe Tomography,” Ultramicroscopy, Vol. 228, p. 113334, Sep. 2021, doi: 10.1016/j.ultramic.2021.113334. 5. A. Zintler, et al.: “FIB based Fabrication of an Operative Pt/HfO2/ TiN Device for Resistive Switching inside a Transmission Electron Microscope,” Ultramicroscopy, Vol. 181, p. 144–149, Oct. 2017, doi: 10.1016/j.ultramic.2017.04.008. 6. O. Recalde, et al.: “Effect of Induced Stimuli on the Leakage Current of Operative Oxide-basedDevices inside a TEM,” Microsc. Microanal., 28(S1), p. 820–821, Aug. 2022, doi: 10.1017/S1431927622003671. 7. S. Ho Oh, et al.: “In situ TEM Observation of Void Formation and Migration inPhaseChangeMemoryDeviceswithConfinedNanoscale Ge2 Sb2 Te5,” Nanoscale Adv., 2(9), p. 3841–3848, 2020, doi: 10.1039/ D0NA00223B. 8. M. Brodovoi, et al.: “In-Situ Electrical Biasing of Electrically Connected TEM Lamellae with Embedded Nanodevices,” in ISTFA 2021, Phoenix, Arizona, Oct. 2021, p. 190–195. doi: 10.31399/asm. cp.istfa2021p0190. 9. Q. Zhong, et al.: “Optimization of the In Situ Biasing FIB Sample PreparationforHafnia-BasedFerroelectricCapacitor,” Micromachines, 12(12), p. 1436, Nov. 2021, doi: 10.3390/mi12121436. 10. D. Cooper and M. Bryan: “Reproducible in-situ Electrical Biasing of Resistive Memory Materials using Piezo-controlled Electrical Contacts and Chip Based Systems,” Microsc. Microanal., 27(S1), p. 164–166, Aug. 2021, doi: 10.1017/S1431927621001197. 11. W.A. Hubbard, et al.: “Nanofilament Formation and Regeneration During Cu/Al2O3 Resistive Memory Switching,” Nano Lett., 15(6), p. 3983–3987, Jun. 2015, doi: 10.1021/acs.nanolett.5b00901. 12. W.A. Hubbard, et al.: “Imaging Dielectric Breakdown in Valence Change Memory,” Adv. Funct. Mater., 32(2), p. 2102313, 2022, doi: 10.1002/adfm.202102313. 13. T.E. Everhart, O.C. Wells, and R.K. Matta: “A Novel Method of Semiconductor Device Measurements,” Proc. IEEE, 52(12), p. 1642–1647, Dec. 1964, doi: 10.1109/PROC.1964.3460. 14. G.M. Johnson and A. Rummel: “Use of Passive, Quantitative EBIC to Characterize Device Turn-on in 7 nm Technology,” Microelectron. Reliab., Vol. 126, p. 114380, Nov. 2021, doi: 10.1016/j. microrel.2021.114380. 15. G. Moldovan and W. Courbat: “Strategies to Identify Physical Origin of Contrast in EBIRCH,” presented at the ISTFA 2022, Pasadena, California, USA, Oct. 2022, p. 277–283. doi: 10.31399/asm. cp.istfa2022p0277. 16. A. Rummel and A.J. Smith: “Nanoprobing at Low Beam Energy, Ad- dressing Current and Future Nodes,” EDFA, 24(2), p. 12–15, May 2022. Fig. 3 ADF STEM and STEM EBIC images of the device in Fig. 2. Both images were acquired simultaneously and therefore show signals from the same region. The EBIC image shows currentmeasured fromthe top electrode, with the current scale shown to the right. The bright EBIC signal is centered on the interface of the p- and n-doped Si layers, indicating the presence of a strong electric field at the interface.
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 8 17. M. Mecklenburg, et al.: “ElectronBeam-inducedCurrent Imagingwith Two-angstromResolution,” Ultramicroscopy, Vol. 207, p. 112852, Dec. 2019, doi: 10.1016/j.ultramic.2019.112852. 18. W.A. Hubbard, et al.: “Scanning Transmission Electron Microscope Mapping of Electronic Transport in Polycrystalline BaTiO3 Ceramic Capacitors,” Appl. Phys. Lett., 115(13), p. 133502, Sep. 2019, doi: 10.1063/1.5117055. 19. M. Mecklenburg, et al.: “Electrical Isolation Preserved by Plasma Focused Ion Beam TEM Sample Preparation and Verified with STEM SEEBIC Imaging,” Microsc. Microanal., p. 1–3, Jul. 2020, doi: 10.1017/ S1431927620013756. ABOUT THE AUTHOR William A. Hubbard received a B.S. in physics and mathematics from Boston University in 2008, after which he worked as a research assistant in the Harvard University Physics Department until 2010. He received his Ph.D. in experimental condensed matter physics in 2017 from UCLA, where he was also a postdoctoral scholar until 2019. He is currently the CEO of NanoElectronic Imaging Inc., where his research focuses on developing electronmicroscopy based techniques, such as STEMEBIC, which can visualize electronic and thermal contrast in operating nanodevices. NOTEWORTHY NEWS FIB SEMMEETING 2023 The 15th annual FIB SEM Meeting will be held June 11-16, in conjunction with IUMAS 8 in Banff, AB Canada. FIB SEM will feature presentations, tutorials, and posters by FIB users and vendors, highlighting new applications and the latest technology. The event offers plenty of technical content as well as opportunities for informal discussions with your FIB colleagues. FIB SEM 2024 will be held back in the Maryland/DC area. For more information, visit fibsem.net or email keana.scott@nist.gov. IRPS 2023 The IEEE International Reliability Physics Symposium’s (IRPS) annual conference will be held March 26-30, 2023, in Monterey, Calif. The IRPS technical program includes technical sessions, keynotes, and invited talks on emerging issues, tutorials, workshops, poster sessions, a year-in-review seminar, and equipment demonstrations. IRPS 2023 is soliciting increased participation in the following areas: circuit reliability and aging, 3D IC advanced packaging, neuromorphic computing; and more. The IRPS Conference is sponsored by the IEEE Reliability Society and IEEE Electron Devices Society. For more information, visit the IRPS website at irps.org and watch for any updates to the meeting plan.
edfas.org 9 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 SCANNING MICROWAVE IMPEDANCE MICROSCOPY: OVERVIEW AND LOW TEMPERATURE OPERATION Nicholas Antoniou PrimeNano Inc., Santa Clara, California nicholas@primenanoinc.com EDFAAO (2023) 1:9-13 1537-0755/$19.00 ©ASM International® INTRODUCTION Scanning microwave impedance microscopy (sMIM) is a relatively recent technology that was invented at Stanford University by Shen and Kelly.[1] It has been commercialized by PrimeNano Inc. as ScanWave and is currently available in five different configurations from room temperature to ultra-low (mK) temperature operation. sMIM is a near-field technique utilizing microwaves to probe the electrical properties of materials such as conductivity and permittivity with nanoscale lateral resolution. Its unique advantage is that electrical property information can be obtainedwithout the use of an electrical current flow through the sample. This not only makes sample preparation simple, but one can image floating dielectrics with no grounding, and image sub-surface features. In Fig. 1, buried islands of silicon dioxide in a sea of silicon nitride are highlighted because of the sensitivity of the systemto permittivity changes in a scanned area. To achieve nanoscale resolution, a customprobe ismounted onto an atomic force microscope (AFM) that enables 2D and 3D image acquisition of relative permittivity, conductivity, and topography information. Low temperature sMIM systems were recently introduced to the market that operate from sub 100 mK to 2 K, with vector magnets and an ultra-high vacuum option. The ability tomeasure the electrical properties of materials at varying temperatures has led to many discoveries such as superconductivity, quantumhall effect, fractional quantum hall effect, giant magnetoresistance, and graphene. Quantum computing research is also benefiting from this low temperature capability as the properties of materials used in quantum computing are often analyzed at the low temperatures at which they operate. This Fig. 2 sMIM system schematic outlining the basic principle of operation. Fig. 1 sMIMcapacitance image (sMIM-C in volts on Z axis) of SiO2 islands buried under 60 nm of Si3N4.
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 10 article describes the principles of operation of sMIM, gives an overview of the low temperature configuration, and highlights applications. PRINCIPLES OF OPERATION In ScanWave, a microwave signal is transmitted to the tip of a custom cantilever with matched impedance and shielding for lownoise operation.[2] The same tip also collects the reflected signal that has been affected by the tip-sample interaction and the collected signal is then processed in the systemelectronics to provide two output signals: sMIM-C and sMIM-R (Fig. 2). The sMIM-C signal, measured in volts, corresponds to the relative capacitance of a nanoscale volume of material directly underneath the tip; and sMIM-R, also a signal in volts, corresponds to the relative resistivity of the same volume of material. As the tip scans the sample surface, driven by an AFM, sample electrical information is obtained simultaneously with topographic information. In addition to the R and C information acquired, dC/dV and dR/dV can be collected by applying an AC signal on top of the RF signal. In a semiconductor, the dC/dV phase indicates the carrier type (n or p) and the amplitude relates to the doping level. Unlike scanning capacitancemicroscopy (SCM), in sMIM one can directly measure dC/dV without sample grounding and collect R and C information. AScanWavesystemincludes thefollowingcomponents: • Shielded probe with impedance matching • Probe interface module to attach the probe to the AFM • Microwave electronics ScanWave has been designed to work on major AFM platforms and is compatible with many AFM scanning modes such as contact mode, tapping mode, and lift mode. Since sMIM is a near-field measurement, resolution below the tip diameter can be achieved. Because of its controlled periodicity, a Moiré pattern is often used to measure resolution in sMIM systems and using this technique, a resolution of about 1 nmwas recently reported.[3] Using a capacitance reference standard, the sensitivity of the system for capacitance was measured to be 0.075 aF. ROOM TEMPERATURE sMIM Room temperature sMIM is used in semiconductor FA and device characterization,[4-6] 2D material characterization, ferroelectrics, subsurface sensing, and more. In one example sMIM was used to isolate gate oxide issues as shown in Fig. 3 where a failing gate oxide test structure was compared to surrounding devices to determine if the failure was a point defect or area contamination.[6] In another study, a highly integrated monolithic silicon PIN (P-type layer, intrinsic layer, N-type layer) diode with a 3D architecture was characterized from substrate to metal using sMIM.[4] Other use cases include locating dopant level related defects that are invisible to electron and optical microscopy, nonlinear material characterization, and nano C-V. LOW TEMPERATURE sMIM Understanding the fundamental properties of materials often requires electrical measurements to be taken at ultra-low temperatures and in the presence of high magnetic fields. This is the case for quantum computing materials, super conductivity, and other materials research areas. Abig challenge inquantumcomputing has been the phenomenon of decoherence that occurs very rapidly and is irreversible; it was discovered that under highmagnetic fields, decoherence time canbe extended.[7] Studies of decoherence and other behaviors of quantum systems are increasingly being conducted at low temperature and under varying magnetic fields. PrimeNano has introduced three types of low temperature sMIM systems that are commercially available turnkey solutions and include superconducting magnets up to 12 Tesla and 3D capabilities: Fig. 3 Study to determine root cause of failing gate oxide test structure. Good vs bad devices that were buried were measured using sMIM C-V and dC/dV.
edfas.org 1 1 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 1. 2KScanWave: sMIMoperated in a dry or liquid cryostat withaheliumexchangegas sampleenvironment. Thebase temperature can reach below 2 K and the system can be operated up to room temperature (300 K). 2. mKScanWave: sMIMoperated inadilution refrigerator. The base temperature can reach below 100 mK and the system can be operated up to 300 mK. 3. UHV ScanWave: sMIM operated in a low temperature, UHV environment. The base temperature can reach be- low500mK and operates up to room temperature (300 K). The sample ismeasured in UHVwith in-situ sample transfer capability. Figure 4 shows the components and wiring of the 2K LT ScanWave system. A low temperature AFM with an sMIM probe interface module is integrated in a cryostat and a laser interferometer is used to detect the cantilever deformation for topographic feedback. The front-end electronics are installed in the cold chamber to minimize noise that may otherwise enter the system from the long wiring required to reach the room temperature part of the electronics. The LT sMIM systems comewith an option to install solenoid magnets or vector magnets that can reach up to 12 Tesla for testing samples under magnetic fields. To reach sub 100 mK, dilution refrigeration is used as shown in Fig. 5a. The insert shown in Fig. 5b holds the AFM stage and ScanWave probe. The probe is inserted, and the sample is mounted on the AFM stage in air and at room temperature before loading the insert from the top. A sample with an array of thin aluminum rectangles surrounded by dielectric was imaged at 90 mK as shown in Fig. 6. The measurement conditions were: 10 µm scan width, 500 nm/s scanning speed, and -10 dB microwave power. The native oxide on the aluminumplate has a different dielectric k-value than the surrounding silicon dioxide and this is imaged with high contrast (hundreds of millivolts, Fig. 6, middle) in the capacitance signal indicating that very high sensitivity is achievable at sub 100 mK. CASE STUDIES QUANTUMWELL DEVICES In the study of quantum spin Hall effects in HgTe quantum wells, modeling predicted that the edge conductivity would disappear once an applied magnetic field reached 3.8 Tesla. However, sMIM images (Fig. 7b and c) taken at a temperature of a few Kelvin and varying magnetic fields demonstrated that the edge conductivity continued to persist well above 3.8 Tesla and even above 9 Tesla.[8] It took an even higher magnetic field for the edge conductivity to become insulating, which indicates that the model did not accurately represent the behavior of this device. PHASE TRANSITION IN MANGANITES Manganites are known to have complex phase diagrams andwhenobserved at themacro scale, twoormore phases can appear to co-exist. Using sMIMat temperatures fromabout 15 K to 250 K andmagnetic fields up to 9 Tesla, conductivity mapping of Nd1/2Sr1/2MnO3 thin films grown Fig. 5 mKelvin system images (a) dilution refrigeration and (b) insert with AFM and ScanWave probe. (a) (b) Fig. 4 Diagram of the 2K LT ScanWave system.
edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 12 on (110) SrTiO3 substrates uncoveredadramatic first-order phase transition with a colossal magnetoresistance from the antiferromagnetic charge/orbital-order insulating state to the ferromagnetic metallic state. With sMIM, researchers observed an orientation-ordered percolating network of domains through the transition.[9] The network has a large periodof ~100 nanometers and the filamentary metallic domains preferentially align along certain crystal axes of the substrate, suggesting that the anisotropic elastic strain from the substrate is a key interaction in this system. DOMAIN WALLS IN MAGNATE In the study of domainwalls inmagnatematerials, the areas to be investigated are often buried under an insulating bulk. By using microwaves, sMIM can image through the insulating material enabling local nanoscale conductivity measurements. In a published study,[10] by using sMIM the researchers were able to show the existence of conductivemagneticdomainwalls inamagnetic insulator. SUMMARY The study of the properties of materials at the nanoscale requires new tools and technologies to enable discoveries and improve our understandingof thephysical world. Scanningmicrowave impedancemicroscopy is one such technology that has been configured to operate in a wide range of temperatures fromsub 100mK to roomtemperature. Usingmicrowaves, electrical properties ofmaterials such as permittivity and conductivity can bemapped at the nanoscale at ultra-low temperatures and under strongmagnetic fields. In addition, ACmeasurements can be taken to determine doping type and concentration in semiconductors. Themicrowave signal also provides sub surface informationwithout any special sample treatment. sMIM is now commercialized and turnkey solutions are offered so that researchers can focus on their research and not equipment building. High sensitivity electronics combined with a shielded probe and impedance matching provide extremely high electrical resolution (0.075 aF capacitance sensitivity) and nanoscale spatial resolution. Until recently, sMIM images have been qualitative in nature but quantification of dopant levels in semi- (a) Fig. 7 Quantumwell behavior under varyingmagnetic fields: (a) device structure, (b) 5.5 nmquantumwell device conductivity vs magnetic filed, and (c) 7.5 nm quantumwell device conductivity vs magnetic field. (b) (c) Fig. 6 An aluminumplate surrounded by SiO2 imaged at sub 100mK. Top image is of topography,middleof sMIM-C (in volts) and bottom is the sMIM-R image (in volts).
edfas.org 13 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 5. B. Drevnoik, et al.: “Extending Electrical Scanning ProbeMicroscopy Measurements of Semiconductor Devices Using Microwave Impedance Microscopy,” Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, p. 82-86, 2015. 6. Wei-Shan Hu, et al.: “Device Dielectric Quality Analysis and Fault Isolation at the Contact Level by Scanning Microwave Impedance Microscopy,” Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, p. 463-467, 2016. 7. S. Takahashi, et al.: “Decoherence in Crystals of QuantumMolecular Magnets,” Nature, 476, 76–79 (2011). 8. E.Y. Ma, et al.: “Unexpected Edge Conduction in Mercury Telluride Quantum Wells under Broken Time-reversal Symmetry,” Nature Communications, Vol. 6, p. 7252, 2016. 9. K. Lai, et al.: “Mesoscopic Percolating Resistance Network in a Strained Manganite Thin Film,” Science, 329(9), p. 190, 2010. 10. E.Y. Ma, et al.: “Mobile Metallic Domain Walls in an All-in-All-Out Magnetic Insulator,” Science, 350(6260), p. 538, 2015. conductors is now offered and in the near-term future other material properties will also be quantified. REFERENCES 1. K. Lai, et al.: “Modeling and Characterization of a Cantilever-based Near-field Scanning Microwave Impedance Microscope,” Review of Scientific Instruments, Vol. 79, p. 063703, 2008. 2. Y. Yang, et al.: “Batch-fabricated Cantilever Probes with Electrical Shielding for Nanoscale Dielectric and Conductivity Imaging,” J. Micromech. Microeng, p. 115040, 2012. 3. D.A.A. Ohlberg, et al.: “The Limits of Near Field ImmersionMicrowave Microscopy Evaluated by Imaging Bilayer GrapheneMoiré Patterns,” Nature Communications, Vol. 12, Article number: 2980 (2021). 4. R.C. Germanicus, et al.: “Mapping of Integrated PIN Diodes with a 3D Architecture by Scanning Microwave Impedance Microscopy and Dynamic Spectroscopy,” Journal of Nanotechnology, No. 11, p. 1764-1775, 2020. ABOUT THE AUTHOR Nicholas Antoniou holds a B.S. and M.S. in electrical engineering from Texas A&M University. He has over 30 years of experience in semiconductors and product management. Antoniou started his career as a process integration and yield enhancement engineer. After 10 years in the fab, he joined FEI Company (now Thermo Fisher) where he managed focused ion beam products. From there he was responsible for the FIB-SEMequipment at HarvardUniversity’s Center for Nanoscale Systems. He returned to productmanagement at NovaMeasuring Instrumentswhere hewas the productmanager of new materials metrology systems. He currently manages PrimeNano’s sMIM ScanWave product line. Antoniou is an active member of EDFAS and co-chairs the EDFAS FA Future Roadmap Council. NOTEWORTHY NEWS IPFA 2023 The 30th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) will be held in July 2023 in Penang, Malaysia. The event will be devoted to the fundamental understanding of the physical characterization techniques and associated technologies that assist in probing the nature of wearout and failure in conventional and newCMOS devices, in turn resulting in improved know-how of the physics of device, circuit, andmodule failure that serves as critical input for future design and reliability. The symposium is technically cosponsored by the IEEE Electron Device Society and IEEE Reliability Society. For more information, visit the IPFA website at ipfa-ieee.org.
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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 16 PROCESSES FOR THINNING AND POLISHING HIGHLY WARPED DIE TO A NEARLY CONSISTENT THICKNESS: PART II Kirk A. Martin RKD Systems, Aptos, California kirk@rkdsystems.org EDFAAO (2023) 1:16-19 1537-0755/$19.00 ©ASM International® INTRODUCTION Part I of this series, published in EDFA, November 2022, deals with the problems and considerations for thinning a large, warpeddie toauniformthickness of 50 +/- 2microns and suggests processes and procedures for obtaining this result. InPart I, it was suggested that insteadof attempting to thin an entire die to a thickness of less than 10microns, the entire die can instead be thinned to 50 microns for initial evaluation. The initial evaluation would result in defining general, rather small areas of interest. The small area of interest would be thinned to the desired, less than 10 microns, remaining silicon thickness. The reasons for thinning largedie to 50microns instead of the desired 1 to 5 microns remaining silicon thickness (RST) were discussed. A large die sample can be processed to 50 microns RST quickly. It will be robust enough to survive de-mounting and can be powered in a test socket. Analysis can be performed that identifies the area of the die that is of interest.[1] The area of interest is then thinned to the desired thickness, leaving the rest of the die thick enough to allow powering the sample. Thinning only a small area significantly reduces processing time and results inamuch more robust sample. In this article, the processes and considerations for locally thinning an area of interest to the desired RST are discussed. THE NEED FOR A ROBUST SAMPLE The forces that cause the die surface to curve are built in when the die is mounted on the substrate. As the die is thinned, the force is redistributed, causing the die surface to flatten when the sample is removed from the holder.[3] This causes increasing compressive strain in the remaining silicon. The force involved does not change but is applied to thinner silicon. At some thickness, the remaining silicon will no longer be able to support the force and the die will fracture. During the thinning process, the forces generated by the process add to the packaging forces. This can cause the die to fracture at greater thickness than the desired RST. Some of the packaging force is distributed to the wax that attaches the substrate to the sample holder. When the sample is de-mounted, most of the packaging forcewill be applied to the silicon. Thinning the entire die could easily cause the die to fracture during de-mounting and make any handling of the sample problematic. An RST of 50 microns should survive de-mounting, insertion in a test socket, or any other post-processing handling required. Locally thinning an area of interest will have little effect on themechanical strength of the sample as long as the area thinned is limited to a small fraction of the die surface. LIMITS ON THE THINNING PROCESSES Each processing step causes some level of damage to the remaining silicon. The depth of the damage is a function of the abrasive size and the down force of the tool. The general rule of thumb is that the bulk material damage extends 1 to 1.5 times the grit size of the abrasive. This indicates that a grinding tool with75-microndiamond should not be used to thin to less than 120 microns RST. The bulk of the silicon can be removed using large grit size if possible, but as the desired endpoint is approached, finer grits should be used. The endpoint for each process step shouldbe at a thickness equal to the final RSTplus the grit size plus the RST tolerance. If the final thickness is to
edfas.org 1 7 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 25 NO . 1 be 1.0 +/- 0.5microns, then a process using 3-micron slurry shouldbe stopped at aminimumthickness of 4.5microns. This requires all but the last two process steps to remove material equal the difference between the last step’s grit size and the previous step’s grit size. This is generallymore removal than isusedprocessing the50-micronsample, but at 50 microns RST, damage that extends a micron or two has no effect on the integrity of the sample. Removing this much material increases the process time but is required to produce a usable result. Increasingpressuremay speedup theprocess but may also increase sample breakage. The strength of the silicon is a function of the cube of the thickness. A 50-micron sample shouldbe able to take 125 times more force than a 10-micron thick sample. The thinner the desired process endpoint, the lower the allowable process force and the finer the permissible abrasive. A typical series of thinning steps, along with starting and ending thicknesses are shown in Tables 1 and 2. It can be seen that the time required to get 1 micron RST is largely the same as 5 micron RST. SELECTING THE SIZE OF THE AREA OF INTEREST The size of the area to be analyzed is determined fromthe evaluation of the 50-micron thick sample. The size of the thinned area must be larger by at least two times the diameter of the tools to be used in the thinning process. If a 2mm square area is needed, and 2 mm diameter tools are to be used, the minimum size of the thinned area should be 6 mm square. Larger is better for several reasons. The outside edge of the total area has the least amount of material removed as it has less time in contact with the tool face. This produces a fillet, or radius, at the intersection of the cavity edge and floor as shown in Fig. 1. This fillet will raise the tool slightlywhen the tool is at the edge causing it to extend further toward the center of the cavity. By then the tool has moved its diameter from the cavity wall; there is no longer any edge effect. Table 1 1 micron final RST Process step Abrasive, microns Starting RST, microns Ending RST, microns Removed, microns Final polish 0.04 1.5 1 0.5 Fine polish 1 4.5 1.5 2.5 Coarse polish 3 10.5 4.5 6 Fine lap 9 21.5 10.5 11 Coarse lap 20 50 21.5 28.5 Table 2 5 micron final RST Process step Abrasive, microns Starting RST, microns Ending RST, microns Removed, microns Final polish 0.04 5.5 5 0.5 Fine polish 1 9 5.5 3.5 Coarse polish 3 15 9 6 Fine lap 9 26 15 11 Coarse lap 20 50 26 24 Fig. 1 The edge fillet is not a radius, but gradually slopes to join the cavity floor. This will lift the tool slightly when it is near the cavity wall, thereby extending the edge distortion toward the center of the work area. Fig. 2 As can be seen, the slope of the area of interest can be faithfully reproduced in the lower end of the cavity. At the upper end, the fillet at the cavitywall will raise the tool creating surface distortion into the area of interest.
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