edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 28 NO. 2 8 fabricated using the inkjet method, in which two silver electrodes are deposited on the chip and contact a via chain. For both deposition methods, an underlying dielectric layer is required to avoid electrical shorting between the fabricated electrodes and the chip under test. This dielectric layer is shown in blue in Figs. 3a and c and must also be patterned to open the region of interest and to create vias that allow the electrodes to contact the probe pads (sized at 80 µm × 60 µm). FABRICATION OF THE DIELECTRIC LAYER To minimize the fabrication complexity of the dielectric layer and ensure compatibility with a FA laboratory environment, a polyimide material was selected, as it can be readily deposited and patterned without the need for advanced processing equipment. The process flow is illustrated in Fig. 4. A thin photo-patternable polyimide layer is first spray‑coated onto the test chip from an aerosol can, resulting in a film thickness between 1.5 and 2.0 µm (Fig. 4a). The layer is subsequently exposed (Fig. 4b) to define openings in the region of interest and to form vias. Maskless lithography can be readily implemented using direct laser exposure at a wavelength of 405 nm, either with a defocused laser beam or, as recently demonstrated at ISTFA 2024, using a modified office projector.[13] After exposure, the sample undergoes development in an aqueous sodium hydroxide solution (Fig. 4c), followed by a curing step on a hot plate at 240°C for 10 min to ensure complete removal of the carrier solvent and to enhance the chemical, electrical, structural, and thermal stability of the polyimide layer. In addition, the curing process induces partial reflow of the polyimide, resulting in smoother via sidewalls (Fig. 4d), which improves layer conformality during subsequent metal deposition. Based on the intended metallization approach, either stencil‑based deposition or inkjet printing is then selected for metal deposition. The total structure thickness (dielectric and conductive layers) measures less than 3 µm and the complete fabrication flow shown in Fig. 4 can be completed within 2 hours. FAILURE ANALYSIS OF A nanoTSV CHAIN Figure 5 shows a photograph of the test chip prepared using the inkjet‑printing sample‑preparation process for the localization of leakage failures in a nanoTSV chain (Fig. 2c) within a backside power‑delivery‑network test vehicle. Electrical contact to the inkjet‑printed probe pads is achieved using low‑profile spring pins. The probe pads (a) (b) (c) (d) (e) (f) Fig. 4 Step‑by‑step fabrication process flow illustrating the creating of the patterned dielectric layer (a, b, c, d) and the on‑chip extension electrodes (e, f).
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